Product Overview

NOVAFAB NANOTWIN Cu is a high-purity copper electroplating process which produces a <111> oriented deposit with a high fraction of nano-twinning. It is specially formulated for use in the fabrication of pillars or pads for wafer level packaging applications that require hybrid bonding. This system enables low temperature, high reliability copper to copper interconnects for die-to-die (D2D), die-to-wafer (D2W), and wafer-to-wafer (W2W) bonding.

NOVAFAB NANOTWIN Cu is a ready to use solution designed for use with soluble or insoluble anodes. The NOVAFAB NANOTWIN Cu process yields excellent thickness distribution over whole wafer surface for consistent electrical properties and bondability.

Features

  • Novel one-part additive system
  • <111> oriented crystal structure
  • High nanotwin density
  • Excellent process stability
  • Wide operating window
  • High purity

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Highly Nanotwinned Columnar Copper

Nano-twinned Cu (nt-Cu) demonstrates superior mechanical and electrical properties. High performance applications are driving I/O pitch reduction and I/O density increases leading to solder removal at reduced pitch sizes.

Plating Copper-Macdermid Alpha

NOVAFAB Nanotwin Cu

Product Name

Cu Packaging Solution

Cu Process Feature

Feature-Property Benefit

NOVAFAB NANOTWIN Cu

Hybrid Bonding

Nanotwin
High purity

KV Low

Key Barrier Materials and Solder Bumps / Caps

  • Pillar/Post, RDL,
  • Viafill, Hybrid bonding
  • Thermal pillar, TSV
MICROFAB EVF NiBAR MICROFAB NI-200 MICROFAB NI-100 MICROFAB TS-650 MICROFAB SN-350 MICROFAB RDLV 50, 60, 70 MICROFAB MP 2500 MICROFAB SPM 1100

Key Barrier Materials and Solder Bumps / Caps

  • Pillar/Post, RDL,
  • Viafill, Hybrid bonding
  • Thermal pillar, TSV
MICROFAB EVF NiBAR MICROFAB NI-200 MICROFAB NI-100 MICROFAB TS-650 MICROFAB SN-350 MICROFAB RDLV 50, 60, 70 MICROFAB MP 2500 MICROFAB SPM 1100

D2D, D2W, W2W Applications and Redistribution Line (RDL)

Die-to-Die, Die-to-Wafer and Wafer-to-Wafer hybrid bonding for sub 40um pitch packages enabling 3D and chiplets resulting in lower power consumption and circuits with greater efficiency that result in lower power consumption.

Wafer Level Packaging System in Package (SiP) Heterogeneous Integration Sensors

D2D, D2W, W2W Applications and Redistribution Line (RDL)

Die-to-Die, Die-to-Wafer and Wafer-to-Wafer hybrid bonding for sub 40um pitch packages enabling 3D and chiplets resulting in lower power consumption and circuits with greater efficiency that result in lower power consumption.

Wafer Level Packaging System in Package (SiP) Heterogeneous Integration Sensors

Hybrid Bonding

High I/O density and fine pitch will require solder removal for void and crack mitigation. Hybrid bonding enables improved electromigration resistance, high reliability, and increased performance for AI, HPC, GPU, image sensors

UBM Backside Metal Wafer Bumping RDL Pillar / Post Hybrid Bonding Thermal Management

Hybrid Bonding

High I/O density and fine pitch will require solder removal for void and crack mitigation. Hybrid bonding enables improved electromigration resistance, high reliability, and increased performance for AI, HPC, GPU, image sensors

UBM Backside Metal Wafer Bumping RDL Pillar / Post Hybrid Bonding Thermal Management

Key Barrier Materials and Solder Bumps / Caps

  • Pillar/Post, RDL,
  • Viafill, Hybrid bonding
  • Thermal pillar, TSV
MICROFAB EVF NiBAR MICROFAB NI-200 MICROFAB NI-100 MICROFAB TS-650 MICROFAB SN-350 MICROFAB RDLV 50, 60, 70 MICROFAB MP 2500 MICROFAB SPM 1100

Key Barrier Materials and Solder Bumps / Caps

  • Pillar/Post, RDL,
  • Viafill, Hybrid bonding
  • Thermal pillar, TSV
MICROFAB EVF NiBAR MICROFAB NI-200 MICROFAB NI-100 MICROFAB TS-650 MICROFAB SN-350 MICROFAB RDLV 50, 60, 70 MICROFAB MP 2500 MICROFAB SPM 1100

D2D, D2W, W2W Applications and Redistribution Line (RDL)

Die-to-Die, Die-to-Wafer and Wafer-to-Wafer hybrid bonding for sub 40um pitch packages enabling 3D and chiplets resulting in lower power consumption and circuits with greater efficiency that result in lower power consumption.

Wafer Level Packaging System in Package (SiP) Heterogeneous Integration Sensors

D2D, D2W, W2W Applications and Redistribution Line (RDL)

Die-to-Die, Die-to-Wafer and Wafer-to-Wafer hybrid bonding for sub 40um pitch packages enabling 3D and chiplets resulting in lower power consumption and circuits with greater efficiency that result in lower power consumption.

Wafer Level Packaging System in Package (SiP) Heterogeneous Integration Sensors

Hybrid Bonding

High I/O density and fine pitch will require solder removal for void and crack mitigation. Hybrid bonding enables improved electromigration resistance, high reliability, and increased performance for AI, HPC, GPU, image sensors

UBM Backside Metal Wafer Bumping RDL Pillar / Post Hybrid Bonding Thermal Management

Hybrid Bonding

High I/O density and fine pitch will require solder removal for void and crack mitigation. Hybrid bonding enables improved electromigration resistance, high reliability, and increased performance for AI, HPC, GPU, image sensors

UBM Backside Metal Wafer Bumping RDL Pillar / Post Hybrid Bonding Thermal Management
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